1. Field of the Invention
The present invention relates to a PCM signal reproducing apparatus. More specifically, the present invention relates to a circuit for generating clock signals of a frequency corresponding to the interval of vertical synchronizing signals in a video tape recorder or the like.
2. Description of the Prior Art
It is well known in the art of video tape recorders, for example, that synchronizing signal components of video signals and PCM'ed audio signals are recorded on a video track on a magnetic tape and the PCM'ed audio signals are reproduced whenever desired. Such PCM reproduction demands clock pulses in order to process the PCM'ed data and obtain audio signals. The thus reproduced PCM signals, however, generally include components whose time axis varies with variations in number of revolutions of a rotary head. Reproduction of those PCM signals thus requires clock pulses the frequency of which is variable depending upon variations in number of revolutions of the rotary head rather than clock pulses of a fixed frequency. One well-known technique for generating these frequency-variable clock pulses is the use of a phase locked loop including a voltage controlled oscillator whose oscillation frequency is varied depending upon variations in the interval of the vertical synchronizing signals. For instance, attachment of any foreign object to a surface of a magnetic tape results in dropout of any of the vertical synchronizing signals which are to be a reference signal for the phase locked loop. In the event that there is such a loss of one or more discrete vertical synchronizing signals in the prior art apparatus, the phase locked loop receiving these vertical synchronizing signals as the reference signals would be placed into unlocked state, making it impossible to reproduce the PCM data. A conventional approach to compensate for such dropout of the vertical synchronizing signals is to generate pseudo synchronizing signals which in turn prevent the phase locked loop from being placed unlocked state due to such dropout. However, such dropout takes place at a period of time where the PCM audio signals are recorded or interposed. Should any dropout take place at a PCM signal multiplexing period, such dropout would be developed from the output of a vertical synchronizing separator circuit including an integration circuit and supplied as the reference input to the phase locked loop. It has been confirmed by the results of the inventor's experiments that any dropout at the PCM multiplexing period also may place the phase lock loop into unlocked state, thus disturbing the clock pulses. No approach has been suggested so far to overcome variations in the clock pulses originating from such dropout at the PCM signal interval.